1. Field
Exemplary embodiments of the present invention relate to an integrated circuit.
2. Description of the Related Art
While the demand for high-speed integrated circuits is increasing, physical limits are being reached in increasing speeds of integration circuits. For example, in the case of a memory device, there is a physical limit as to a further decrease in access time for a core region (a memory cell array region). To overcome such physical limits, the memory device may increase the speed of an input/output operation by internally processing data in parallel and serially outputting data. Here, a memory device uses a parallel-to-serial converter to convert parallel-processed internal data into serial data and output the serial data to outside a chip. Here, a variety of integrated circuits other than the memory device may perform parallel-to-serial data conversion within the chip (system).
FIG. 1 is a timing diagram illustrating an operation of converting four parallel data into serial data.
A parallel-to-serial conversion is achieved by sequentially transferring data loaded on a plurality of transfer lines P0 to P3 to a single line S. As illustrated in FIG. 1, in a case in which data D0 to D3 are loaded on four transfer lines P0 to P3, the data of the four lines P0 to P3 may be transferred to the output line S one by one. Therefore, signals CK0 to CK3 determining the points of time to transfer the data D0 to D3 aligned on the transfer lines P0 to P3 to the output line S are generated and used in the parallel-to-serial conversion.
In operation, the data D0 of the line P0 is transferred to the line S at the point of time when the signal CK0 is activated, and the data D1 of the line P1 is transferred to the line S at the point of time when the signal CK1 is activated. Also, the data D2 of the line P2 is transferred to the line S at the point of time when the signal CK2 is activated, and the data D3 of the line P3 is transferred to the line S at the point of time when the signal CK3 is activated.
As described above, the parallel-to-serial conversion is achieved by sequentially transferring data loaded on the plurality of transfer lines to the output line. Therefore, the signals determining the points of time to transfer the data from the plurality of transfer lines to the output line (hereinafter, referred to as transmission signals) are used. In the case of 2N:1 parallel-to-serial conversion, in particular, 4:1 or 8:1 parallel-to-serial conversion, the signals determining the points of time to transfer data can be simply generated by using a clock to generate four transmission signals. For example, as shown in FIG. 1, transmission signals CK0, CK1, CK2 and CK3 may be generated by using a clock CLK.
In the case of the 4:1 or 8:1 parallel-to-serial conversion using the transmission signals CK0, CK1, CK2 and CK3 generated by using the clock CLK to generate four transmission signals, where the order of the transmission signals CK0, CK1, CK2 and CK3 match the order of output data. For example, the first (or fifth) data outputted in response to a command (hereinafter, referred to as start data) is always outputted at the point of time when transmission signal CK0 is activated. Therefore, the start data is outputted at the point of time when transmission signal CK0 is activated.
A DDR4 semiconductor memory device uses a burst length (BL) of 10 bits, where ten bits of data is serially outputted at a time and thus, 10:1 parallel-to-serial conversion is to be performed in a parallel-to-serial converter. Here, the clock is divided into 2N transmission signals. Therefore, transmission signals CK0, CK1, CK2 and CK3 generated by using the clock CLK may be used in the 10:1 parallel-to-serial conversion.
FIG. 2 is a timing diagram illustrating an operation of converting ten bits of parallel data into serial data by using transmission signals CK0, CK1, CK2 and CK3 generated by using a clock CLK.
In a process of outputting data in response to the first command, start data D0 is aligned with transmission signal CK0 and is transferred to an output line S. In a process of outputting data in response to the second command, start data D0′ is aligned with transmission signal CK2 and is transferred to the output line S.
That is, the transmission signal transferring the start data to the line S is periodically changed. Therefore, in a case in which ten bits of data are successively outputted in response to successively inputted commands, the transmission signal transferring the start data is to be changed successively. If the parallel-to-serial conversion circuit for such a scheme is implemented within the integrated circuit, the complexity thereof may increase. In addition, if the integrated circuit is to output eight bits of data by using the parallel-to-serial conversion circuit and perform additional functions in the parallel-to-serial conversion circuit, the complexity of the parallel-to-serial conversion circuit will exponentially increase. As a result, the occupied area and complexity of the integrated circuit will also exponentially increase.